CVE-2023-46835

The current setup of the quarantine page tables assumes that the<br /> quarantine domain (dom_io) has been initialized with an address width<br /> of DEFAULT_DOMAIN_ADDRESS_WIDTH (48) and hence 4 page table levels.<br /> <br /> However dom_io being a PV domain gets the AMD-Vi IOMMU page tables<br /> levels based on the maximum (hot pluggable) RAM address, and hence on<br /> systems with no RAM above the 512GB mark only 3 page-table levels are<br /> configured in the IOMMU.<br /> <br /> On systems without RAM above the 512GB boundary<br /> amd_iommu_quarantine_init() will setup page tables for the scratch<br /> page with 4 levels, while the IOMMU will be configured to use 3 levels<br /> only, resulting in the last page table directory (PDE) effectively<br /> becoming a page table entry (PTE), and hence a device in quarantine<br /> mode gaining write access to the page destined to be a PDE.<br /> <br /> Due to this page table level mismatch, the sink page the device gets<br /> read/write access to is no longer cleared between device assignment,<br /> possibly leading to data leaks.<br />