CVE-2026-43191

*** Pendiente de traducción *** In the Linux kernel, the following vulnerability has been resolved:<br /> <br /> drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS on DCN35<br /> <br /> [Why]<br /> A backport of the change made for DCN401 that addresses an issue where<br /> we turn off the PHY PLL when disabling TMDS output, which causes the<br /> OTG to remain stuck.<br /> <br /> The OTG being stuck can lead to a hang in the DCHVM&amp;#39;s ability to ACK<br /> invalidations when it thinks the HUBP is still on but it&amp;#39;s not receiving<br /> global sync.<br /> <br /> The transition to PLL_ON needs to be atomic as there&amp;#39;s no guarantee<br /> that the thread isn&amp;#39;t pre-empted or is able to complete before the<br /> IOMMU watchdog times out.<br /> <br /> [How]<br /> Backport the implementation from dcn401 back to dcn35.<br /> <br /> There&amp;#39;s a functional difference in when the eDP output is disabled in<br /> dcn401 code so we don&amp;#39;t want to utilize it directly.